; * ---------------------------------------------------------------------------------------
; *  @file:    startup_MKL25Z4.s
; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
; *            MKL25Z4
; *  @version: 2.5
; *  @date:    2015-2-19
; *  @build:   b150602
; * ---------------------------------------------------------------------------------------
; *
; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without modification,
; * are permitted provided that the following conditions are met:
; *
; * o Redistributions of source code must retain the above copyright notice, this list
; *   of conditions and the following disclaimer.
; *
; * o Redistributions in binary form must reproduce the above copyright notice, this
; *   list of conditions and the following disclaimer in the documentation and/or
; *   other materials provided with the distribution.
; *
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
; *   contributors may be used to endorse or promote products derived from this
; *   software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/


                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset

                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors
                EXPORT  __Vectors_End
                EXPORT  __Vectors_Size
                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|

__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
                DCD     Reset_Handler  ; Reset Handler
                DCD     NMI_Handler                         ;NMI Handler
                DCD     HardFault_Handler                   ;Hard Fault Handler
                DCD     0                                   ;Reserved
                DCD     0                                   ;Reserved
                DCD     0                                   ;Reserved
                DCD     0                                   ;Reserved
                DCD     0                                   ;Reserved
                DCD     0                                   ;Reserved
                DCD     0                                   ;Reserved
                DCD     SVC_Handler                         ;SVCall Handler
                DCD     0                                   ;Reserved
                DCD     0                                   ;Reserved
                DCD     PendSV_Handler                      ;PendSV Handler
                DCD     SysTick_Handler                     ;SysTick Handler

                                                            ;External Interrupts
                DCD     DMA0_IRQHandler                     ;DMA channel 0 transfer complete
                DCD     DMA1_IRQHandler                     ;DMA channel 1 transfer complete
                DCD     DMA2_IRQHandler                     ;DMA channel 2 transfer complete
                DCD     DMA3_IRQHandler                     ;DMA channel 3 transfer complete
                DCD     Reserved20_IRQHandler               ;Reserved interrupt
                DCD     FTFA_IRQHandler                     ;Command complete and read collision
                DCD     LVD_LVW_IRQHandler                  ;Low-voltage detect, low-voltage warning
                DCD     LLWU_IRQHandler                     ;Low leakage wakeup Unit
                DCD     I2C0_IRQHandler                     ;I2C0 interrupt
                DCD     I2C1_IRQHandler                     ;I2C1 interrupt
                DCD     SPI0_IRQHandler                     ;SPI0 single interrupt vector for all sources
                DCD     SPI1_IRQHandler                     ;SPI1 single interrupt vector for all sources
                DCD     UART0_IRQHandler                    ;UART0 status and error
                DCD     UART1_IRQHandler                    ;UART1 status and error
                DCD     UART2_IRQHandler                    ;UART2 status and error
                DCD     ADC0_IRQHandler                     ;ADC0 interrupt
                DCD     CMP0_IRQHandler                     ;CMP0 interrupt
                DCD     TPM0_IRQHandler                     ;TPM0 single interrupt vector for all sources
                DCD     TPM1_IRQHandler                     ;TPM1 single interrupt vector for all sources
                DCD     TPM2_IRQHandler                     ;TPM2 single interrupt vector for all sources
                DCD     RTC_IRQHandler                      ;RTC alarm
                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
                DCD     PIT_IRQHandler                      ;PIT interrupt
                DCD     Reserved39_IRQHandler               ;Reserved interrupt
                DCD     USB0_IRQHandler                     ;USB0 interrupt
                DCD     DAC0_IRQHandler                     ;DAC0 interrupt
                DCD     TSI0_IRQHandler                     ;TSI0 interrupt
                DCD     MCG_IRQHandler                      ;MCG interrupt
                DCD     LPTMR0_IRQHandler                   ;LPTMR0 interrupt
                DCD     Reserved45_IRQHandler               ;Reserved interrupt
                DCD     PORTA_IRQHandler                    ;PORTA Pin detect
                DCD     PORTD_IRQHandler                    ;PORTD Pin detect
				DCD     DefaultISR                                    ;48
				DCD     DefaultISR                                    ;49
				DCD     DefaultISR                                    ;50
				DCD     DefaultISR                                    ;51
				DCD     DefaultISR                                    ;52
				DCD     DefaultISR                                    ;53
				DCD     DefaultISR                                    ;54
				DCD     DefaultISR                                    ;55
				DCD     DefaultISR                                    ;56
				DCD     DefaultISR                                    ;57
				DCD     DefaultISR                                    ;58
				DCD     DefaultISR                                    ;59
				DCD     DefaultISR                                    ;60
				DCD     DefaultISR                                    ;61
				DCD     DefaultISR                                    ;62
				DCD     DefaultISR                                    ;63
				DCD     DefaultISR                                    ;64
				DCD     DefaultISR                                    ;65
				DCD     DefaultISR                                    ;66
				DCD     DefaultISR                                    ;67
				DCD     DefaultISR                                    ;68
				DCD     DefaultISR                                    ;69
				DCD     DefaultISR                                    ;70
				DCD     DefaultISR                                    ;71
				DCD     DefaultISR                                    ;72
				DCD     DefaultISR                                    ;73
				DCD     DefaultISR                                    ;74
				DCD     DefaultISR                                    ;75
				DCD     DefaultISR                                    ;76
				DCD     DefaultISR                                    ;77
				DCD     DefaultISR                                    ;78
				DCD     DefaultISR                                    ;79
				DCD     DefaultISR                                    ;80
				DCD     DefaultISR                                    ;81
				DCD     DefaultISR                                    ;82
				DCD     DefaultISR                                    ;83
				DCD     DefaultISR                                    ;84
				DCD     DefaultISR                                    ;85
				DCD     DefaultISR                                    ;86
				DCD     DefaultISR                                    ;87
				DCD     DefaultISR                                    ;88
				DCD     DefaultISR                                    ;89
				DCD     DefaultISR                                    ;90
				DCD     DefaultISR                                    ;91
				DCD     DefaultISR                                    ;92
				DCD     DefaultISR                                    ;93
				DCD     DefaultISR                                    ;94
				DCD     DefaultISR                                    ;95
				DCD     DefaultISR                                    ;96
				DCD     DefaultISR                                    ;97
				DCD     DefaultISR                                    ;98
				DCD     DefaultISR                                    ;99
				DCD     DefaultISR                                    ;100
				DCD     DefaultISR                                    ;101
				DCD     DefaultISR                                    ;102
				DCD     DefaultISR                                    ;103
				DCD     DefaultISR                                    ;104
				DCD     DefaultISR                                    ;105
				DCD     DefaultISR                                    ;106
				DCD     DefaultISR                                    ;107
				DCD     DefaultISR                                    ;108
				DCD     DefaultISR                                    ;109
				DCD     DefaultISR                                    ;110
				DCD     DefaultISR                                    ;111
				DCD     DefaultISR                                    ;112
				DCD     DefaultISR                                    ;113
				DCD     DefaultISR                                    ;114
				DCD     DefaultISR                                    ;115
				DCD     DefaultISR                                    ;116
				DCD     DefaultISR                                    ;117
				DCD     DefaultISR                                    ;118
				DCD     DefaultISR                                    ;119
				DCD     DefaultISR                                    ;120
				DCD     DefaultISR                                    ;121
				DCD     DefaultISR                                    ;122
				DCD     DefaultISR                                    ;123
				DCD     DefaultISR                                    ;124
				DCD     DefaultISR                                    ;125
				DCD     DefaultISR                                    ;126
				DCD     DefaultISR                                    ;127
				DCD     DefaultISR                                    ;128
				DCD     DefaultISR                                    ;129
				DCD     DefaultISR                                    ;130
				DCD     DefaultISR                                    ;131
				DCD     DefaultISR                                    ;132
				DCD     DefaultISR                                    ;133
				DCD     DefaultISR                                    ;134
				DCD     DefaultISR                                    ;125
				DCD     DefaultISR                                    ;136
				DCD     DefaultISR                                    ;137
				DCD     DefaultISR                                    ;138
				DCD     DefaultISR                                    ;139
				DCD     DefaultISR                                    ;140
				DCD     DefaultISR                                    ;141
				DCD     DefaultISR                                    ;142
				DCD     DefaultISR                                    ;143
				DCD     DefaultISR                                    ;144
				DCD     DefaultISR                                    ;145
				DCD     DefaultISR                                    ;146
				DCD     DefaultISR                                    ;147
				DCD     DefaultISR                                    ;148
				DCD     DefaultISR                                    ;149
				DCD     DefaultISR                                    ;150
				DCD     DefaultISR                                    ;151
				DCD     DefaultISR                                    ;152
				DCD     DefaultISR                                    ;153
				DCD     DefaultISR                                    ;154
				DCD     DefaultISR                                    ;155
				DCD     DefaultISR                                    ;156
				DCD     DefaultISR                                    ;157
				DCD     DefaultISR                                    ;158
				DCD     DefaultISR                                    ;159
				DCD     DefaultISR                                    ;160
				DCD     DefaultISR                                    ;161
				DCD     DefaultISR                                    ;162
				DCD     DefaultISR                                    ;163
				DCD     DefaultISR                                    ;164
				DCD     DefaultISR                                    ;165
				DCD     DefaultISR                                    ;166
				DCD     DefaultISR                                    ;167
				DCD     DefaultISR                                    ;168
				DCD     DefaultISR                                    ;169
				DCD     DefaultISR                                    ;170
				DCD     DefaultISR                                    ;171
				DCD     DefaultISR                                    ;172
				DCD     DefaultISR                                    ;173
				DCD     DefaultISR                                    ;174
				DCD     DefaultISR                                    ;175
				DCD     DefaultISR                                    ;176
				DCD     DefaultISR                                    ;177
				DCD     DefaultISR                                    ;178
				DCD     DefaultISR                                    ;179
				DCD     DefaultISR                                    ;180
				DCD     DefaultISR                                    ;181
				DCD     DefaultISR                                    ;182
				DCD     DefaultISR                                    ;183
				DCD     DefaultISR                                    ;184
				DCD     DefaultISR                                    ;185
				DCD     DefaultISR                                    ;186
				DCD     DefaultISR                                    ;187
				DCD     DefaultISR                                    ;188
				DCD     DefaultISR                                    ;189
				DCD     DefaultISR                                    ;190
				DCD     DefaultISR                                    ;191
				DCD     DefaultISR                                    ;192
				DCD     DefaultISR                                    ;193
				DCD     DefaultISR                                    ;194
				DCD     DefaultISR                                    ;195
				DCD     DefaultISR                                    ;196
				DCD     DefaultISR                                    ;197
				DCD     DefaultISR                                    ;198
				DCD     DefaultISR                                    ;199
				DCD     DefaultISR                                    ;200
				DCD     DefaultISR                                    ;201
				DCD     DefaultISR                                    ;202
				DCD     DefaultISR                                    ;203
				DCD     DefaultISR                                    ;204
				DCD     DefaultISR                                    ;205
				DCD     DefaultISR                                    ;206
				DCD     DefaultISR                                    ;207
				DCD     DefaultISR                                    ;208
				DCD     DefaultISR                                    ;209
				DCD     DefaultISR                                    ;210
				DCD     DefaultISR                                    ;211
				DCD     DefaultISR                                    ;212
				DCD     DefaultISR                                    ;213
				DCD     DefaultISR                                    ;214
				DCD     DefaultISR                                    ;215
				DCD     DefaultISR                                    ;216
				DCD     DefaultISR                                    ;217
				DCD     DefaultISR                                    ;218
				DCD     DefaultISR                                    ;219
				DCD     DefaultISR                                    ;220
				DCD     DefaultISR                                    ;221
				DCD     DefaultISR                                    ;222
				DCD     DefaultISR                                    ;223
				DCD     DefaultISR                                    ;224
				DCD     DefaultISR                                    ;225
				DCD     DefaultISR                                    ;226
				DCD     DefaultISR                                    ;227
				DCD     DefaultISR                                    ;228
				DCD     DefaultISR                                    ;229
				DCD     DefaultISR                                    ;230
				DCD     DefaultISR                                    ;231
				DCD     DefaultISR                                    ;232
				DCD     DefaultISR                                    ;233
				DCD     DefaultISR                                    ;234
				DCD     DefaultISR                                    ;235
				DCD     DefaultISR                                    ;236
				DCD     DefaultISR                                    ;237
				DCD     DefaultISR                                    ;238
				DCD     DefaultISR                                    ;239								
__Vectors_End
    AREA    BootloaderConfig, DATA, READONLY
	IF		BL_HAS_BOOTLOADER_CONFIG == 1
        ;__bootloaderConfigurationArea ; 0x3c0
		DCD     0x6766636b    ; [00:03] tag - 'kcfg' Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'.
        DCD     0xFFFFFFFF    ; [04:07] crcStartAddress
        DCD     0xFFFFFFFF    ; [08:0b] crcByteCount
        DCD     0xFFFFFFFF    ; [0c:0f] crcExpectedValue
        DCB     0xFF          ; [10:10] enabledPeripherals
        DCB     0xFF          ; [11:11] i2cSlaveAddress
        DCW     5000           ; [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
        DCW     0xFFFF        ; [14:15] usbVid
        DCW     0xFFFF        ; [16:17] usbPid
        DCD     0xFFFFFFFF    ; [18:1b] usbStringsPointer
        DCB     0xFF          ; [1c:1c] clockFlags - High Speed and other clock options
        DCB     0xFF          ; [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
        DCW     0xFFFF        ; [1e:1f] reserved
        ; Fill to align with flash configuration field. 
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF			
        DCD     0xFFFFFFFF        ; Reserved for user TRIM value
	ELSE      
        ; Fill to align with flash configuration field. 
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF
        DCD     0xFFFFFFFF     			
        DCD     0xFFFFFFFF      ; Reserved for user TRIM value
	ENDIF // BL_HAS_BOOTLOADER_CONFIG

__Vectors_Size 	EQU     __Vectors_End - __Vectors

; <h> Flash Configuration
;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
;   <i> and security information that allows the MCU to restrict access to the FTFL module.
;   <h> Backdoor Comparison Key
;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
BackDoorK0      EQU     0xFF
BackDoorK1      EQU     0xFF
BackDoorK2      EQU     0xFF
BackDoorK3      EQU     0xFF
BackDoorK4      EQU     0xFF
BackDoorK5      EQU     0xFF
BackDoorK6      EQU     0xFF
BackDoorK7      EQU     0xFF
;   </h>
;   <h> Program flash protection bytes (FPROT)
;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
;     <i> Each bit protects a 1/32 region of the program flash memory.
;     <h> FPROT0
;       <i> Program Flash Region Protect Register 0
;       <i> 1/32 - 8/32 region
;       <o.0>   FPROT0.0
;       <o.1>   FPROT0.1
;       <o.2>   FPROT0.2
;       <o.3>   FPROT0.3
;       <o.4>   FPROT0.4
;       <o.5>   FPROT0.5
;       <o.6>   FPROT0.6
;       <o.7>   FPROT0.7
nFPROT0         EQU     0x00
FPROT0          EQU     nFPROT0:EOR:0xFF
;     </h>
;     <h> FPROT1
;       <i> Program Flash Region Protect Register 1
;       <i> 9/32 - 16/32 region
;       <o.0>   FPROT1.0
;       <o.1>   FPROT1.1
;       <o.2>   FPROT1.2
;       <o.3>   FPROT1.3
;       <o.4>   FPROT1.4
;       <o.5>   FPROT1.5
;       <o.6>   FPROT1.6
;       <o.7>   FPROT1.7
nFPROT1         EQU     0x00
FPROT1          EQU     nFPROT1:EOR:0xFF
;     </h>
;     <h> FPROT2
;       <i> Program Flash Region Protect Register 2
;       <i> 17/32 - 24/32 region
;       <o.0>   FPROT2.0
;       <o.1>   FPROT2.1
;       <o.2>   FPROT2.2
;       <o.3>   FPROT2.3
;       <o.4>   FPROT2.4
;       <o.5>   FPROT2.5
;       <o.6>   FPROT2.6
;       <o.7>   FPROT2.7
nFPROT2         EQU     0x00
FPROT2          EQU     nFPROT2:EOR:0xFF
;     </h>
;     <h> FPROT3
;       <i> Program Flash Region Protect Register 3
;       <i> 25/32 - 32/32 region
;       <o.0>   FPROT3.0
;       <o.1>   FPROT3.1
;       <o.2>   FPROT3.2
;       <o.3>   FPROT3.3
;       <o.4>   FPROT3.4
;       <o.5>   FPROT3.5
;       <o.6>   FPROT3.6
;       <o.7>   FPROT3.7
nFPROT3         EQU     0x00
FPROT3          EQU     nFPROT3:EOR:0xFF
;     </h>
;   </h>
;   <h> Flash nonvolatile option byte (FOPT)
;     <i> Allows the user to customize the operation of the MCU at boot time.
;     <o.0> LPBOOT0
;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
;       <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
;     <o.2> NMI_DIS
;       <0=> NMI interrupts are always blocked
;       <1=> NMI_b pin/interrupts reset default to enabled
;     <o.3> RESET_PIN_CFG
;       <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
;       <1=> RESET_b pin is dedicated
;     <o.4> LPBOOT1
;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
;       <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
;     <o.5> FAST_INIT
;       <0=> Slower initialization
;       <1=> Fast Initialization
FOPT          EQU     0xFF
;   </h>
;   <h> Flash security byte (FSEC)
;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
;     <o.0..1> SEC
;       <2=> MCU security status is unsecure
;       <3=> MCU security status is secure
;         <i> Flash Security
;     <o.2..3> FSLACC
;       <2=> Freescale factory access denied
;       <3=> Freescale factory access granted
;         <i> Freescale Failure Analysis Access Code
;     <o.4..5> MEEN
;       <2=> Mass erase is disabled
;       <3=> Mass erase is enabled
;     <o.6..7> KEYEN
;       <2=> Backdoor key access enabled
;       <3=> Backdoor key access disabled
;         <i> Backdoor Key Security Enable
FSEC          EQU     0xFE
;   </h>
; </h>
                IF      :LNOT::DEF:RAM_TARGET
                AREA    FlashConfig, DATA, READONLY
__FlashConfig
                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
                ENDIF


                AREA    |.text|, CODE, READONLY

; Reset Handler

Reset_Handler   PROC
                EXPORT  Reset_Handler             [WEAK]
                IMPORT  SystemInit
                IMPORT  init_data_bss
                IMPORT  __main

                IF      :LNOT::DEF:RAM_TARGET
                REQUIRE FlashConfig
				REQUIRE BootloaderConfig
                ENDIF

                CPSID   I               ; Mask interrupts
                LDR     R0, =SystemInit
                BLX     R0
                LDR     R0, =init_data_bss
                BLX     R0
                CPSIE   i               ; Unmask interrupts
                LDR     R0, =__main
                BX      R0
                ENDP


; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
                PROC
                EXPORT  NMI_Handler         [WEAK]
                B       .
                ENDP
HardFault_Handler\
                PROC
                EXPORT  HardFault_Handler         [WEAK]
                B       .
                ENDP
SVC_Handler\
                PROC
                EXPORT  SVC_Handler         [WEAK]
                B       .
                ENDP
PendSV_Handler\
                PROC
                EXPORT  PendSV_Handler         [WEAK]
                B       .
                ENDP
SysTick_Handler\
                PROC
                EXPORT  SysTick_Handler         [WEAK]
                B       .
                ENDP
Default_Handler\
                PROC
                EXPORT  DMA0_IRQHandler         [WEAK]
                EXPORT  DMA1_IRQHandler         [WEAK]
                EXPORT  DMA2_IRQHandler         [WEAK]
                EXPORT  DMA3_IRQHandler         [WEAK]
                EXPORT  Reserved20_IRQHandler         [WEAK]
                EXPORT  FTFA_IRQHandler         [WEAK]
                EXPORT  LVD_LVW_IRQHandler         [WEAK]
                EXPORT  LLWU_IRQHandler         [WEAK]
                EXPORT  I2C0_IRQHandler         [WEAK]
                EXPORT  I2C1_IRQHandler         [WEAK]
                EXPORT  SPI0_IRQHandler         [WEAK]
                EXPORT  SPI1_IRQHandler         [WEAK]
                EXPORT  UART0_IRQHandler         [WEAK]
                EXPORT  UART1_IRQHandler         [WEAK]
                EXPORT  UART2_IRQHandler         [WEAK]
                EXPORT  ADC0_IRQHandler         [WEAK]
                EXPORT  CMP0_IRQHandler         [WEAK]
                EXPORT  TPM0_IRQHandler         [WEAK]
                EXPORT  TPM1_IRQHandler         [WEAK]
                EXPORT  TPM2_IRQHandler         [WEAK]
                EXPORT  RTC_IRQHandler         [WEAK]
                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
                EXPORT  PIT_IRQHandler         [WEAK]
                EXPORT  Reserved39_IRQHandler         [WEAK]
                EXPORT  USB0_IRQHandler         [WEAK]
                EXPORT  DAC0_IRQHandler         [WEAK]
                EXPORT  TSI0_IRQHandler         [WEAK]
                EXPORT  MCG_IRQHandler         [WEAK]
                EXPORT  LPTMR0_IRQHandler         [WEAK]
                EXPORT  Reserved45_IRQHandler         [WEAK]
                EXPORT  PORTA_IRQHandler         [WEAK]
                EXPORT  PORTD_IRQHandler         [WEAK]
                EXPORT  DefaultISR         [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLWU_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
Reserved39_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTMR0_IRQHandler
Reserved45_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
DefaultISR
                LDR    R0, =DefaultISR
                BX     R0
                ENDP
                  ALIGN


                END
